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| AT29C257 Features * * * * * * * * * * * * Fast Read Access Time - 70 ns 5-Volt-Only Reprogramming Page Program Operation Single Cycle Reprogram (Erase and Program) Internal Address and Data Latches for 64-Bytes Internal Program Control and Timer Hardware and Software Data Protection Fast Program Cycle Times Page (64-Byte) Program Time - 10 ms Chip Erase Time - 10 ms DATA Polling for End of Program Detection Low Power Dissipation 50 mA Active Current 300 A CMOS Standby Current Typical Endurance > 10,000 Cycles Single 5V 10% Supply CMOS and TTL Compatible Inputs and Outputs Pin-Compatible with AT29C010A and AT29C512 for Easy System Upgrades 256K (32K x 8) 5-volt Only CMOS Flash Memory Description The AT29C257 is a 5-volt-only in-system Flash programmable and erasable read only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 275 mW. When the device is deselected, the CMOS standby current is less than 300 A. The device endurance is such that any sector can typically be written to in excess of 10,000 times. To allow for simple in-system reprogrammability, the AT29C257 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from a static RAM. Reprogramming the AT29C257 is performed on a page basis; 64-bytes of data are loaded into the device and then simultaneously programmed. The contents of the entire device may be erased by using a 6-byte software code (although erasure before programming is not needed). During a reprogram cycle, the address locations and 64-bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the page and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected a new access for a read, program or chip erase can begin. AT29C257 Pin Configurations Pin Name A0 - A14 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don't Connect PLCC Top View 0012K 4-105 Block Diagram Device Operation READ: The AT29C257 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention. BYTE LOAD: A byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Byte loads are used to enter the 64-bytes of a page to be programmed or the software codes for data protection and chip erasure. PROGRAM: The device is reprogrammed on a page basis. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded during the programming of its page will be indeterminate. Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high to low transition on WE (or CE) within 150 s of the low to high transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 150 s of the last low to high transition, the load period will end and the internal programming period will start. A6 to A14 specify the page address. The page address must be valid during each high to low transition of WE (or CE). A0 to A5 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation. SOFTWARE DATA PROTECTION: A software controlled data protection feature is available on the AT29C257. Once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. The software protection feature may be enabled or disabled by the user; when shipped from Atmel, the software data protection feature is disabled. To enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. After the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. All software program commands must obey the page program timing specifications. Once set, the software data protection feature remains active unless its disable command is issued. Power transitions will not reset the software data protection feature, however the software feature will guard against inadvertent program cycles during power transitions. Once set, software data protection will remain active unless the disable command sequence is issued. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, a read operation will effectively be a polling operation. After the software data protection's 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. The 64-bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. (continued) 4-106 AT29C257 AT29C257 Device Operation (Continued) HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT29C257 in the following ways: (a) VCC sense-- if VCC is below 3.8V (typical), the program function is inhibited. (b) VCC power on delay-- once VCC has reached the VCC sense level, the device will automatically time out 5 ms (typical) before programming. (c) Program inhibit-- holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter-- pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer and may be accessed by a hardware or software operation. For details, see Operating Modes or Software Product Identification. DATA POLLING: The AT29C257 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: I n a d d i t i o n t o DATA p o l l i n g t h e AT29C257 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. OPTIONAL CHIP ERASE MODE: The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details. Absolute Maximum Ratings* Temperature Under Bias................. -55C to +125C Storage Temperature...................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ................... -0.6V to +6.25V All Output Voltages with Respect to Ground .............-0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ................... -0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4-107 DC and AC Operating Range AT29C257-70 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 5V 5% AT29C257-90 0C - 70C -40C - 85C 5V 10% AT29C257-12 0C - 70C -40C - 85C 5V 10% AT29C257-15 0C - 70C -40C - 85C 5V 10% Operating Modes Mode Read Program (2) CE VIL VIL VIL VIH X X X VIL OE VIL VIH VIH X (1) X VIL VIH VH (3) WE VIH VIL VIL X VIH X X VIL Ai Ai Ai Ai X I/O DOUT DIN High Z 5V Chip Erase Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable High Voltage Chip Erase Product Identification Hardware Software (5) High Z X A1 - A14 = VIL, A9 = VH, A0 = VIL A1 - A14 = VIL, A9 = VH, A0 = VIH A0 = VIL A0 = VIH High Z Manufacturer Code (4) Device Code (4) Manufacturer Code (4) Device Code (4) VIL VIL VIH Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V 0.5V. 4. Manufacturer Code: 1F, Device Code: DC 5. See details under Software Product Identification Entry/Exit. DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH1 VOH2 Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS IOL = 2.1 mA IOH = -400 A IOH = -100 A; VCC = 4.5V 2.4 4.2 2.0 .45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f= 5 MHz; IOUT = 0 mA Min Max 10 10 300 3 50 0.8 Units A A A mA mA V V V V V 4-108 AT29C257 AT29C257 AC Read Characteristics AT29C257-70 Symbol tACC tCE (1) tOE (2) tDF (3, 4) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first 0 0 0 Min Max AT29C257-90 Min Max AT29C257-12 Min Max AT29C257-15 Min Max Units ns ns ns ns ns 70 70 40 25 0 0 0 90 90 40 25 0 0 0 120 120 50 30 0 0 0 150 150 70 40 AC Read Waveforms (1, 2, 3, 4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC . 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC . 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level Output Test Load tR, tF < 5 ns Pin Capacitance (f = 1 MHz, T = 25C) (1) Typ CIN COUT Note: Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 4 8 1. This parameter is characterized and is not 100% tested. 4-109 AC Byte Load Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 90 35 0 100 Max Units ns ns ns ns ns ns ns ns AC Byte Load Waveforms WE Controlled CE Controlled 4-110 AT29C257 AT29C257 Program Cycle Characteristics Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 100 0 50 35 0 90 150 Min Max 10 Units ms ns ns ns ns ns s ns Program Cycle Waveforms (1, 2, 3) Notes: 1. A6 through A14 must specify the page address during each high to low transition of WE (or CE). 2. OE must be high when WE and CE are both low. 3. All bytes that are not loaded within the page being programmed will be indeterminate. 4-111 Software Data (1) Protection Enable Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA TO (4) PAGE (64 BYTES) Software Data (1) Protection Disable Algorithm LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA TO (4) PAGE (64 BYTES) WRITES ENABLED ENTER DATA PROTECT STATE (2) Notes for software program code: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Data Protect state will be activated at end of program cycle. 3. Data Protect state will be deactivated at end of program period. 4. 64-bytes of data must be loaded. EXIT DATA PROTECT STATE (3) Software Protected Program Cycle Waveform (1, 2, 3) Notes: 1. A6 through A14 must specify the page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high when WE and CE are both low. 3. All bytes that are not loaded within the page being programmed will be indeterminate. 4-112 AT29C257 AT29C257 Data Polling Characteristics Symbol tDH tOEH tOE tWR Parameter Data Hold Time OE Hold Time OE to Output Delay (2) (1) Min 0 10 0 Typ Max Units ns ns ns ns Write Recovery Time Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. Data Polling Waveforms Toggle Bit Characteristics Symbol tDH tOEH tOE tOEHP tWR Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time (1) Min 0 10 (2) Typ Max Units ns ns ns ns ns 150 0 Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. Toggle Bit Waveforms (1, 2, 3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 4-113 Software Product (1) Identification Entry LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 Software Product (1) Identification Exit LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 PAUSE 10 mS ENTER PRODUCT IDENTIFICATION (2, 3, 5) MODE PAUSE 10 mS EXIT PRODUCT IDENTIFICATION (4) MODE Notes for software product identification: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A14 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1F Device Code: DC 4-114 AT29C257 AT29C257 4-115 Ordering Information tACC (ns) 70 ICC (mA) Active Standby Ordering Code AT29C257-70JC AT29C257-70JI AT29C257-90JC AT29C257-90JI AT29C257-12JC AT29C257-12JI AT29C257-15JC AT29C257-15JI Package 32J 32J 32J 32J 32J 32J 32J 32J Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C) 50 50 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 90 50 50 120 50 50 150 50 50 Package Type 32J 32 Lead, Plastic J-Leaded Chip Carrier (PLCC) 4-116 AT29C257 |
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